1. Field of the Invention
This invention relates to a microcomputer apparatus, and more particularly, to a memory accessing control apparatus that permits a central processing unit and a cathode ray tube controller to access a memory in a time sharing manner.
2. Description of the Prior Art
In microcomputer systems, the output is frequently displayed on a cathode ray tube (CRT). The data to be displayed can be stored in a video-random access memory (video-RAM) which is accessed by a CRT controller in a direct memory access (DMA) operation.
The central processing unit (CPU) supplies the data to the video-RAM for display. The CRT can flicker if the CPU accesses the video-RAM at the same time that the CRT controller tries to access the video-RAM in a DMA operation. The flicker on the screen of the CRT is undesirable and detracts from the operation of the microcomputer system.
Various methods have been suggested to avoid flickering of the CRT. In one method, the CPU accesses the video-RAM during the fly-back period of the CRT scan when the CRT controller does not access the video-RAM. In another prior art method, the CRT controller and the CPU access the video-RAM in a time sharing manner. In a third prior art method, the CPU cycle-steals with respect to the CRT controller, so that the CRT displays the same data for an extended period of time.
The suggested methods a not completely satisfactory in dealing with the flicker problem of the CRT. According to the first method, the CPU processing must be interrupted so that it can access the video-RAM during the fly-back period of the CRT scan. When the CPU and the CRT controller have time sharing access to the video-RAM, a high speed RAM is required. If the system clock frequency is 4 MHz, the video-RAM must have an access time of about 50 n. sec. The cycle-stealing method can be implemented most easily with a synchronous working CPU such as a 6800-type, in which the machine cycles are equally timed from one clock. It is quite difficult to implement a cycle-stealing operation with an asynchronous working CPU, such as Zilog, Inc. models 8080 or ZOA, in which various machine cycles have different numbers of clock pulses allocated thereto.